DSP56367 datasheet(88/100 Pages) FREESCALE

88 / 100 page

Electrical Design Considerations

DSP56367 Technical Data, Rev. 2.1

5-2

Freescale Semiconductor

•

To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that

surface has a proper heat sink.

•

To define a value approximately equal to a junction-to-board thermal resistance, the thermal

resistance is measured from the junction to where the leads are attached to the case.

•

If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance

is computed using the value obtained by the equation: (TJ – TT)/PD.

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the

first definition. From a practical standpoint, that value is also suitable for determining the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will estimate a junction temperature slightly hotter than actual

temperature. Hence, the new thermal metric, thermal characterization parameter or

JT, has been defined

to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection

when using the surface temperature of the package. Remember that surface temperature readings of

packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and

to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge

thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

5.2

Electrical Design Considerations

CAUTION

This device contains circuitry protecting against damage due to high static

voltage or electrical fields. However, normal precautions should be taken to

avoid exceeding maximum voltage ratings. Reliability of operation is

enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,

either GND or VCC). The suggested value for a pull-up or pull-down resistor

is 10 k ohm.

Use the following list of recommendations to assure correct DSP operation:

•

Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from

the board ground to each GND pin.

•

Use at least six 0.01–0.1

µF bypass capacitors positioned as close as possible to the four sides of

the package to connect the VCC power source to GND.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and

GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.

•

Use at least a four-layer PCB with two inner layers for VCC and GND.

•

Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.

This recommendation particularly applies to the address and data buses as well as the IRQA,

IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are

recommended.

DSP56367 데이터시트(PDF) 88 Page - Freescale Semiconductor, Inc

DSP56367 데이터시트(HTML) 88 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

데이터시트 다운로드

링크 URL