68HC05PL4 datasheet(25/98 Pages) FREESCALE

25 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

INTERRUPTS

REV 2.0

4-1

SECTION 4

INTERRUPTS

The CPU can be interrupted by ve different sources – one software and four

hardware:

•

Non-maskable Software Interrupt Instruction (SWI)

•

External Asynchronous Interrupt (IRQ)

•

16-Bit Timer

•

8-Bit Timer

•

Keyboard Interrupt

4.1

INTERRUPT VECTORS

Table 4-1

summarizes the reset and interrupt sources and vector assignments

Table 4-1. Vector Address for Interrupts and Reset

Function

Source

Local

Mask

Global

Mask

Priority

(1=Highest)

Vector

Address

Reset

Power-On Logic

None

$1FFE-$1FFF

RESET Pin

None

COP Watchdog

COPON1

SWI

User Code

None

Same Priority

As Instruction

$1FFC-$1FFD

External IRQ

IRQ Pin

IRQEN

I Bit

$1FFA-$1FFB

16-Bit Timer

ICF Bit

ICIE

I Bit

$1FF8-$1FF9

TCF Bit

TCIE

OCF Bit

OCIE

8-Bit Timer

T8IF Bit

T8IE

I Bit

$1FF6-$1FF7

Keyboard

KIF3 Bit

KIE3

I Bit

$1FF4-$1FF5

KIF2 Bit

KIE2

KIF1 Bit

KIE1

KIF0 Bit

KIE0

Reserved

—

$1FF2-$1FF3

Reserved

—

$1FF0-$1FF1

NOTES:

1. COPON enables/disables the COP watchdog timer.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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