68HC05PL4 datasheet(67/98 Pages) FREESCALE

67 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

DIGITAL TO ANALOG CONVERTER

REV 2.0

11-1

SECTION 11

DIGITAL TO ANALOG CONVERTER

This section describes Digital-to-Analog module used for DTMF generation.

11.1

DAC CONTROL AND DATA REGISTER

DACEN - DAC Channel Enable

Ths read/write bit enables/disables the DAC module for DTMF output.

1 = Enable DAC module and con gure PA1/DTMF as DTMF output pin.

0 = Disable DAC module and con gure PA1/DTMF as general purpose

PA1 pin.

DA5-DA0

These bits determine the output voltage of the DAC channel. The output volt-

age value is determined by:

VOUT = (VDD x DA[0:5]) x 26

There are 64 evenly spaced voltage levels available between VDD and VSS. The

lowest voltage is VSS and the highest voltage is 63/64VDD.

11.2

DAC OPERATION DURING WAIT MODE

In WAIT mode, the DAC continues to output a xed voltage level which is set by

the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur-

ther power saving is required in WAIT mode.

11.3

DAC OPERATION DURING STOP MODE

In STOP mode, the DAC continues to output a x ed voltage level which is set by

the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur-

ther power saving is required in STOP mode.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DACDR R

DACEN

DA5

DA4

DA3

DA2

DA1

DA0

$000F

reset:

00000000

Figure 11-1. DAC Control and Data Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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