68HC05PL4 datasheet(18/98 Pages) FREESCALE

18 / 98 page

GENERAL RELEASE SPECIFICATION

April 30, 1998

MEMORY

MC68HC05PL4

2-2

REV 2.0

2.2

I/O REGISTERS

The rst 32 addresses of the memor y space, $0000-$001F, are the I/O section.

One I/O register is located outside the 32-byte I/O section, which is the Computer

Operating Properly (COP) register mapped at $1FF0.

The bit assignment of each I/O register is described in the respective sections and

summarized in Figure 2-3 and Figure 2-4.

2.3

RAM

The 256 addresses from $0020 to $01FF serve as both user RAM and the stack

RAM. The CPU uses v e RAM bytes to save all CPU register contents before pro-

cessing an interrupt. During a subroutine call, the CPU uses two bytes to store the

return address. The stack pointer decrements during pushes and increments dur-

ing pulls.

NOTE

Be careful when using nested subroutines or multiple interrupt levels. The CPU

may overwrite data in the RAM during a subroutine or during the interrupt stacking

operation.

2.4

ROM

The 4096 bytes of user ROM is located from address $0E00 to $1DFF.

Addresses $1FF0 to $1FFF contain 16 bytes of ROM reserved for user vectors.

2.5

COP WATCHDOG REGISTER (COPR)

Writing “0” to the COPC bit in the COP watchdog register ($1FF0) resets the COP

watchdog timer. This is a write only register; writing a “1” to COPC has no effect.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

COPR

$1FF0 W

COPC

RESET

UUUUUUUU

Figure 2-2. COP Watchdog Register (COPR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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