68HC05PL4 datasheet(26/98 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

April 30, 1998

INTERRUPTS

MC68HC05PL4

4-2

REV 2.0

NOTE

If more than one interrupt request is pending, the CPU fetches the vector of the

higher priority interrupt rst. A higher priority interrupt does not actually interrupt a

lower priority interrupt service routine unless the lower priority interrupt service

routine clears the I bit.

4.2

INTERRUPT PROCESSING

The CPU does the following actions to begin servicing an interrupt:

•

Stores the CPU registers on the stack in the order shown in

Figure 4-1

•

Sets the I bit in the condition code register to prevent further interrupts

•

Loads the program counter with the contents of the appropriate interrupt

vector locations as shown in Table 4-1

The return from interrupt (RTI) instruction causes the CPU to recover its register

contents from the stack as shown in Figure 4-1. The sequence of events caused

by an interrupt is shown in the o w chart in Figure 4-2

$0020

(Bottom of RAM)

$0021

$00BE

$00BF

$00C0

(Bottom of Stack)

$00C1

$00C2

Unstacking

Order

⇓

Condition Code Register

n+1

Accumulator

n+2

Index Register

n+3

Program Counter (High Byte)

n+4

Program Counter (Low Byte)

⇑

Stacking

$00FD

Order

$00FE

$00FF

Top of Stack (RAM)

Figure 4-1. Interrupt Stacking Order

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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