68HC05PL4 datasheet(17/98 Pages) FREESCALE

17 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

MEMORY

REV 2.0

2-1

SECTION 2

MEMORY

This section describes the organization of the memory on the MC68HC05PL4.

2.1

MEMORY MAP

The CPU can address 8k-bytes of memory space as shown in Figure 2-1. The

ROM portion of the memory holds the program instructions, xed data, user

de ned v ectors, and interrupt service routines. The RAM portion of memory holds

variable data. I/O registers are memory mapped so that the CPU can access their

locations in the same way that it accesses all other memory locations.

Figure 2-1. MC68HC05PL4 Memory Map

I/O REGISTERS

32 BYTES

USER RAM

256 BYTES

UNUSED

USER ROM

4096 BYTES

SELF-CHECK ROM

496 BYTES

$0000

$001F

$0020

$011F

$0120

$0DFF

$0E00

$1DFF

$1E00

$1FEF

$1FFF

$1FF0

$00C0

$00FF

STACK

64 BYTES

USER VECTORS

16 BYTES

RESERVED

KEYBOARD

8-BIT TIMER

16-BIT TIMER

IRQ

SWI

RESET

$1FF0-$1FF1

$1FF2-$1FF3

$1FF4-$1FF5

$1FF6-$1FF7

$1FF8-$1FF9

$1FFA-$1FFB

$1FFC-$1FFD

$1FFE-$1FFF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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