68HC05PL4 datasheet(75/98 Pages) FREESCALE

75 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

INSTRUCTION SET

REV 2.0

12-7

12.1.13 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the rst 256 bytes of memory. Port

registers, port data direction registers, timer registers, and on-chip RAM locations

are in the rst 256 b ytes of memory. The CPU can also test and branch based on

the state of any bit in any of the rst 256 memory locations. Bit manipulation

instructions use direct addressing. Table 12-4 lists these instructions.

12.1.14 Control Instructions

These register reference instructions control CPU operation during program

execution. Control instructions, listed in Table 12-5, use inherent addressing.

Table 12-4. Bit Manipulation Instructions

Instruction

Mnemonic

Clear Bit

BCLR

Branch if Bit Clear

BRCLR

Branch if Bit Set

BRSET

Set Bit

BSET

Table 12-5. Control Instructions

Instruction

Mnemonic

Clear Carry Bit

CLC

Clear Interrupt Mask

CLI

No Operation

NOP

Reset Stack Pointer

RSP

Return from Interrupt

RTI

Return from Subroutine

RTS

Set Carry Bit

SEC

Set Interrupt Mask

SEI

Stop Oscillator and Enable IRQ Pin

STOP

Software Interrupt

SWI

Transfer Accumulator to Index Register

TAX

Transfer Index Register to Accumulator

TXA

Stop CPU Clock and Enable Interrupts

WAIT

Freescale Semiconductor, Inc.

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