68HC05PL4 datasheet(57/98 Pages) FREESCALE

57 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

16-BIT PROGRAMMABLE TIMER

REV 2.0

9-7

The planned action on the TCMP depends on the value stored in the OLVL bit in

the TCR, and it occurs when the value of the 16-bit free-running timer counter

matches the value in the output compare registers shown in Figure 9-3. These

registers are read/write bits and are unaffected by reset.

Writing to the OCRH before writing to the OCRL inhibits timer compares until the

OCRL is written. Reading or writing to the OCRL after reading the TCR will clear

the output compare ag bit (OCF). The output compare OLVL state will be clocked

to its output latch regardless of the state of the OCF.

Figure 9-8. Timer Output Compare Block Diagram

To prevent OCF from being set between the time it is read and the time the output

compare registers are updated, use the following procedure:

1. Disable interrupts by setting the I bit in the condition code register.

2. Write to the OCRH. Compares are now inhibited until OCRL is written.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OCRH

OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0

$0016

reset:

UUUUUUUU

OCRL

OCRL7

OCRL6

OCRL5

OCRL4

OCRL3

OCRL2

OCRL1

OCRL0

$0017

reset:

UUUUUUUU

U = UNAFFECTED BY RESET

Figure 9-9. Output Compare Registers (OCRH, OCRL)

OCRH ($0016)

16-BIT COUNTER

÷ 4

INTERNAL

(XTAL ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

OUTPUT COMPARE

RESET

CLOCK

INTERRUPT

OCRL ($0017)

TIMER STATUS REG.

$0012

$0013

INTERNAL

($FFFC)

DATA

R/W

OCRH

R/W

OCRL

BUS

EDGE

SELECT

DETECT

LOGIC

16-BIT COMPARATOR

(OCF)

TCMP

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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