68HC05PL4 datasheet(74/98 Pages) FREESCALE

74 / 98 page

GENERAL RELEASE SPECIFICATION

April 30, 1998

INSTRUCTION SET

MC68HC05PL4

12-6

REV 2.0

third byte to the program counter if the speci ed bit tests tr ue. The bit to be tested

and its condition (set or clear) is part of the opcode. The span of branching is from

–128 to +127 from the address of the next location after the branch instruction.

The CPU also transfers the tested bit to the carry/borrow bit of the condition code

Table 12-3. Jump and Branch Instructions

Instruction

Mnemonic

Branch if Carry Bit Clear

BCC

Branch if Carry Bit Set

BCS

Branch if Equal

BEQ

Branch if Half-Carry Bit Clear

BHCC

Branch if Half-Carry Bit Set

BHCS

Branch if Higher

BHI

Branch if Higher or Same

BHS

Branch if IRQ Pin High

BIH

Branch if IRQ Pin Low

BIL

Branch if Lower

BLO

Branch if Lower or Same

BLS

Branch if Interrupt Mask Clear

BMC

Branch if Minus

BMI

Branch if Interrupt Mask Set

BMS

Branch if Not Equal

BNE

Branch if Plus

BPL

Branch Always

BRA

Branch if Bit Clear

BRCLR

Branch Never

BRN

Branch if Bit Set

BRSET

Branch to Subroutine

BSR

Unconditional Jump

JMP

Jump to Subroutine

JSR

Freescale Semiconductor, Inc.

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