68HC05PL4 datasheet(73/98 Pages) FREESCALE

73 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

INSTRUCTION SET

REV 2.0

12-5

12.1.11 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and

write the modi ed v alue back to the memory location or to the register. The test for

negative or zero instruction (TST) is an exception to the read-modify-write

sequence because it does not write a replacement value. Table 12-2 lists the

read-modify-write instructions.

12.1.12 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program

counter. The unconditional jump instruction (JMP) and the jump to subroutine

instruction (JSR) have no register operand. Branch instructions allow the CPU to

interrupt the normal sequence of the program counter when a test condition is

met. If the test condition is not met, the branch is not performed. All branch

instructions use relative addressing.

Bit test and branch instructions cause a branch based on the state of any

readable bit in the rst 256 memor y locations. These three-byte instructions use a

combination of direct addressing and relative addressing. The direct address of

the byte to be tested is in the byte following the opcode. The third byte is the

signed offset byte. The CPU nds the conditional br anch destination by adding the

Table 12-2. Read-Modify-Write Instructions

Instruction

Mnemonic

Arithmetic Shift Left

ASL

Arithmetic Shift Right

ASR

Clear Bit in Memory

BCLR

Set Bit in Memory

BSET

Clear

CLR

Complement (One’s Complement)

COM

Decrement

DEC

Increment

INC

Logical Shift Left

LSL

Logical Shift Right

LSR

Negate (Two’s Complement)

NEG

Rotate Left through Carry Bit

ROL

Rotate Right through Carry Bit

ROR

Test for Negative or Zero

TST

Freescale Semiconductor, Inc.

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