68HC05PL4 datasheet(39/98 Pages) FREESCALE

부품명	68HC05PL4

상세설명	Industry standard 8-bit M68HC05 CPU core

PDF	98 Pages

Scroll/Zoom	100%

제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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39 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

RESETS

REV 2.0

5-7

5.5

RESET CHARACTERISTICS

Table 5-1. Reset Characteristics

Figure 5-6. Stop Recovery Timing Diagram

Characteristic

Symbol

Min

Typ

Max

Unit

POR Recovery Voltage2

VPOR

—

100

POR VDD Slew Rate2

Rising2

Falling2

SVDDR

SVDDF

—

0.1

0.05

V/ms

RESET Pulse Width (when bus clock active)

tRL

1.5

—

tCYC

RESET Pulldown Pulse Width (from internal reset)

tRPD

3—4

tCYC

Note:

1. +2.0 ≤ VDD ≤ +4.0 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted

2. By design, not tested.

PCH

NEW

1FFE

tRL

OSC11

RESET

Internal

Clock3

Internal

Address

Bus3

4096

NOTES:

1. Represents the internal gating of the OSC1 pin

2. Normal delay of 4064 tCYC

3. Internal timing signal and data information not available externally.

Internal

Data

Bus3

1FFF

NEW PCH NEW PCL

PCL

NEW

code

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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