68HC05PL4 datasheet(46/98 Pages) FREESCALE

46 / 98 page

GENERAL RELEASE SPECIFICATION

April 30, 1998

INPUT/OUTPUT PORTS

MC68HC05PL4

7-2

REV 2.0

Table 7-1. I/O Pin Functions

7.1.1 Port Data Registers

Each port I/O pin has a corresponding bit in the Port Data Register. When a port

I/O pin is programmed as an output the state of the corresponding data register bit

determines the state of the output pin.

When a port pin is programmed as an input, any read of the Port Data Register

will return the logic state of the corresponding I/O pin. The locations of the Data

Registers for Port A, B, and C are at $0000, $0001 and $0002. The Port Data

Registers are unaffected by reset.

7.1.2 Port Data Direction Registers

Each port I/O pin may be programmed as an input by clearing the corresponding

bit in the DDR, or programmed as an output by setting the corresponding bit in the

DDR. The DDR for Port A, B, and C are located at $0005, $0006 and $0007. The

DDRs are cleared by reset.

NOTE

A “glitch” can be generated on an I/O pin when changing it from an input to an

output unless the data register is rst preconditioned to the desired state before

changing the corresponding DDR bit from a zero to a one.

7.2

PORT A

Port A is an 7-bit bidirectional port, with pins shared with other modules. The

Port A Data Register is at address $0000 and the Data Direction Register is at

address $0005. Port pins PA5 and PA6 are high current sink pins; see Electrical

Speci cations section f or values.

Pin PA0 is only available on MC68HC05PL4. OSC2 replaces PA0 on

MC68HC05PL4B.

Pin PA1 becomes the DTMF output from the DAC when the DACEN bit is set in

the DAC Control and Data Register ($000F).

Pins PA2 and PA3 become the 16-bit timer TCAP and TCMP respectively, when

TCAPEN and TCMPEN are set in the Miscellaneous Control/Status Register

($001C).

R/W

DDR

I/O Pin Functions

The I/O pin is in input mode. Data is written into the output data latch.

Data is written into the output data latch and output to the I/O pin.

The state of the I/O pin is read.

The I/O pin is in an output mode. The output data latch is read.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC05PL4 데이터시트(PDF) 46 Page - Freescale Semiconductor, Inc

68HC05PL4 데이터시트(HTML) 46 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

데이터시트 다운로드

링크 URL