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ORCA ORSPI4 Data Sheet

SPIA_TX128_BE[15:0]

FPGA

→ Core

Byte enables indicating which bytes within the 128-bit word are valid.

Bit[15]-Byte enable for SPIA_TX128_DATA[127:120]

Bit[14]-Byte enable for SPIA_TX128_DATA[119:112]

Bit[13]-Byte enable for SPIA_TX128_DATA[111:104]

Bit[12]-Byte enable for SPIA_TX128_DATA[103:96]

Bit[11]-Byte enable for SPIA_TX128_DATA[95:88]

Bit[10]-Byte enable for SPIA_TX128_DATA[87:80]

Bit[9]-Byte enable for SPIA_TX128_DATA[79:72]

Bit[8]-Byte enable for SPIA_TX128_DATA[71:64]

Bit[7]-Byte enable for SPIA_TX128_DATA[63:56]

Bit[6]-Byte enable for SPIA_TX128_DATA[55:48]

Bit[5]-Byte enable for SPIA_TX128_DATA[47:40]

Bit[4]-Byte enable for SPIA_TX128_DATA[39:32]

Bit[3]-Byte enable for SPIA_TX128_DATA[31:24]

Bit[2]-Byte enable for SPIA_TX128_DATA[23:16]

Bit[1]-Byte enable for SPIA_TX128_DATA[15:8]

Bit[0]-Byte enable for SPIA_TX128_DATA[7:0]

If no BE bits are asserted for a particular location within the DPRAM, data

will be dropped and no write to the DPRAM will occur.

According to the SPI-4.2 speciﬁcation, the BE bits must be asserted for all

but the last transfer, where an End of Packet or Error may occur. The valid

combinations of BE are as follows:

BE[15:0] = 1111111111111111--indicates all sixteen bytes contain valid

user data. If an EOP is present, it resides within the sixteenth byte.

BE[15:0] = 1111111111111110--indicates ﬁfteen bytes are valid. EOP

occurs in ﬁfteenth Byte.

BE[15:0] = 1111111111111100--indicates fourteen bytes are valid. EOP

occurs in fourteenth Byte.

BE[15:0] = 1111111111111000-indicates thirteen byte is valid. EOP occurs

in thirteenth Byte.

BE[15:0] = 1111111111110000--indicates twelve bytes are valid. EOP

occurs in twelfth Byte.

BE[15:0] = 1111111111100000-indicates eleven bytes are valid. EOP

occurs in eleventh Byte.

BE[15:0] = 1111111111000000--indicates ten bytes are valid. EOP occurs

in tenth Byte.

BE[15:0] = 1111111110000000--indicates nine bytes are valid. EOP occurs

in ninth Byte.

BE[15:0] = 1111111100000000--indicates eight bytes are valid. EOP

occurs in eight Byte.

BE[15:0] = 1111111000000000--indicates seven bytes are valid. EOP

occurs in seventh Byte.

BE[15:0] = 1111110000000000--indicates six bytes are valid. EOP occurs

in sixth Byte.

BE[15:0] = 1111100000000000-indicates ﬁve byte is valid. EOP occurs in

ﬁfth Byte.

BE[15:0] = 1111000000000000--indicates four bytes are valid. EOP occurs

in fourth Byte.

BE[15:0] = 1110000000000000-indicates three bytes are valid. EOP

occurs in third Byte.

BE[15:0] = 1100000000000000--indicates two bytes are valid. EOP occurs

in second Byte.

BE[15:0] = 1000000000000000--indicates one byte is valid. EOP occurs in

ﬁrst Byte.

SPIA_TX128_SOP

FPGA

→ Core

Start of Packet indicator. A '1' indicates the start of packet for a particular

port. When operating in 128-bit mode, the SOP indicator must be asserted

coincident with the ﬁrst line write to the FIFO partition in order to align the

start of packet data with the SOP sideband signal.

Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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