ORSPI4 datasheet(85/263 Pages) LATTICE

85 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

The SPI4 status channel operates at 1/8th the SPI4 data rate which is reasonable because data is always sent in

16-byte bursts. Thus the fastest status update can be expected once in every 8 data clock cycles. For a given port,

the frequency with which its status is reported to the far-end transmitter source depends on the allocated band-

width for the port. It is imperative that the transmitter and receiver devices are programmed with identical calendar

sequences. The following examples illustrate this:

Suppose a channelized STS-48 has three STS-12 ports and four STS-3 ports (channels), each STS-12 port

should have four times the bandwidth of an STS-3 port and 12 times the bandwidth of an STS-1 port within a single

calendar cycle. The ﬁrst step is to map each port to an 8-bit port ID (address) as shown in Table 23

Table 23. Port ID Mapping

The calendar sequence is as follows:

A1, A2, A3, B1, A1, A2, A3, B2, A1, A2, A3, B3, A1, A2, A3, B4

The number of calendar entries is thus 16. This calendar sequence is programmed in the receive calendar memory

as follows:

• This example uses the main calendar. The calendar memory is selected by setting the RX_CAL_MEM_SEL bit

(address 30917 in SPIA and address 30A17 in SPIB) to ‘1’.

• Writes are done to addresses 0x31000 - 0x3100F. This will correspond to entries 0x00 - 0x0F in the calendar

memory. This is shown in Table 24. Note that the main calendar memory has 1023 locations and can be pro-

grammed through addresses 0x31000 - 0x313FE. The shadow calendar memory also has 1023 locations and

can be programmed through addresses 0x31400 - 0x317FE.

• After programming the calendar memory, the RX_CAL_MEM_SET bit is set to ‘0’.

• The calendar length register RX_CAL_LEN_MAIN is set to 16 (address 30901 and 30902 in SPIA, 30A01 and

30A02 in SPIB).

• RX_CAL_M_MAIN (address 30900 in SPIA and 30A00 in SPIB) is set to the number of times the calendar

sequence needs to be repeated between framing patterns.

• The shadow calendar can be programmed in the same identical fashion as the main calendar using the steps

described above.

To enable hitless switching between main and shadow calendar memories, the RX_CAL_SW_EN bit (address

30916 in SPIA and 30A16 in SPIB) should be set to ‘1’. This will cause the receive status logic to insert the calen-

dar select word after the framing pattern. The RX_CAL_SEL bit then selects main (bit set to ‘0’) or shadow (bit set

to ‘1’) calendar to be sent on the outgoing status frame. It is important to enable this feature in the transmit device

on the other end of the SPI4 link by setting TX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) to ‘1’.

This will cause the far-end transmit status logic to detect the calendar select word after the framing pattern.

Port

Bandwidth

8-Bit Port ID

(Port Address)

STS-12

0x00

STS-12

0x01

STS-12

0x02

STS-3

0x03

STS-3

0x04

STS-3

0x05

STS-3

0x06

ORSPI4 데이터시트(PDF) 85 Page - Lattice Semiconductor

ORSPI4 데이터시트(HTML) 85 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL