ORSPI4 datasheet(45/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Table 5. FIFO Address Based on Programmed Virtual FIFOs

Table 6. Possible Combinations of Aggregation Modes

Within the embedded core, data is quad-word aligned, and written to the DPRAMs only on 128-bit boundaries.

When operating in 32-bit or 64-bit mode, with the exception of EOP terminated write accesses, either 4 or 2 write

accesses, respectively, must be performed before the internal FIFO address pointer can be incremented to the next

location. It is required for the FPGA to perform all data writes on 128-bit boundaries. Thus, the application will write

entire “lines” to the DPRAM causing the internal address pointer to increment to the next location in memory. If the

FPGA attempts to write to a FIFO partition within the DPRAM and none of the 16 BE bits are set, the data will not

be written into the FIFO and the internal write pointers will not be advanced. This is done to prevent erroneous data

from being sent across the SPI4 link, as well as optimize FIFO memory usage.

Link Disable

Under certain circumstances, the application may require the SPI4 interface to disable a particular DPRAM from

being serviced. To accommodate this, the user can assert the proper 'Link Disable” (LINK_DIS) signal indicating to

the DPRAM logic to stop service to a particular DPRAM. As long as the assertion of the LINK_DIS for a particular

partition is asserted, all partitions within the associated DPRAM will not be serviced. If the application attempts to

perform further writes to any of the disabled FIFO partitions, data will be accepted up to the point the FIFO

becomes full. After the FIFO ﬁlls, data will no longer be accepted. Data written to the disabled DPRAM will remain

latent within the memory. Upon removal of the Link Disable signal, ports from the enabled DPRAM will be serviced

according to the conﬁgured Calendar sequence.

The following is an example of the effect of asserting a Link Disable. For this example, assume the ORSPI4 is con-

ﬁgured as follows:

SPI[A,B]_TX_ADDR[2:0]

Description

XXX

Bits are ignored when the DPRAM is conﬁgured to support a single partition.

(Device Select bits can be set to any value in single partition mode).

000

Selects Partition 0 when the DPRAM is conﬁgured to support 2, 4 or 8 partitions.

001

Selects Partition 1 when the DPRAM is conﬁgured to support 2, 4 or 8 partitions.

010

Selects Partition 2 when the DPRAM is conﬁgured to support 4 or 8 partitions.

011

Selects Partition 3 when the DPRAM is conﬁgured to support 4 or 8 partitions.

100

Selects Partition 4 when the DPRAM is conﬁgured to support 8 partitions.

101

Selects Partition 5 when the DPRAM is conﬁgured to support 8 partitions.

110

Selects Partition 6 when the DPRAM is conﬁgured to support 8 partitions.

111

Selects Partition 7 when the DPRAM is conﬁgured to support 8 partitions.

Mode

Valid

Banks 0 to 3 in 32-bit aggregation mode

Yes

Banks 0, 1 in 64-bit aggregation mode,

Banks 2,3 in 64-bit mode

Yes

Banks 0,1 in 64-bit mode,

Banks 2 & 3 in 32-bit mode

Yes

Banks 0,1 in 32-bit mode,

Banks 2 & 3 in 64-bit mode

Yes

All banks in 128-bit

Yes

Bank 0 in 32-bit mode,

Bank 1 in 64-bit mode or vice-versa

Bank 2 in 32-bit mode,

Bank 3 in 64-bit mode or vice-versa

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