ORSPI4 datasheet(91/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

the idle cycles, the core continues to provide read data. The ASTOP_ON_EOPj signal can be asserted anytime

and held high for any length of time during a read data transfer.

At any time, the user can poll for the status of a FIFO within a DPRAM bank by providing just the read address

SPIA_RX64_ADDR_j without providing the read enable. Note that the timing diagram shown in Figure 36, Figure

37 and Figure 38 indicate a FIFO size of 32 locations. Each location contains two 64-bit data words. Thus when

SPIA_RX64_FIFO_EMPTY_j ﬂag is ‘1’ and RX_DPRAM_EMPTY_TYPE_SELA[j] software register bit in address

30920 is set to ‘1’, it implies that the FIFO has 7 two-word data left (1/4 * 32 locations - 1).

As shown in Figure 38, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be

asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until the clock cycle when

EOP is asserted. However, the user is always required to use the ERR signal in conjunction with the EOP signal.

Irrespective of the ERR signal being asserted, the core always transmits the entire packet. Thus, it is relevant for

the user application to sample the ERR signal simultaneously with EOP. Users should also be aware that this is in

asymmetry with the transmit SPI4 core’s behavior. In the transmit direction, user always asserts ERR signal during

an EOP only. Thus, if any loopback is performed from the receive SPI4 (A or B) to the transmit SPI4 (A or B), the

user should ensure that the received ERR signal is not wired directly to the corresponding transmit ERR signal, but

follows the transmit protocol of providing an ERR signal only in the same clock cycle as an EOP and not earlier.

Figure 36. Read Timing with ASTOP_ON_EOP Deasserted - 64-Bit Mode

….

FIFO size = 32

SPIA_RX64_CLK_j

SPIA_RX64_RD_j

SPIA_RX64_ADDR_j

Address changed to

partition/FIFO p during

last 2-word burst in

address n

SPIA_RX64_FIFO_EMPTY_j

Indicates FIFO has seven

2-word bursts

FIFO empty

low

for address p

Port ID

SPIA_RX64_DATA_j[63:0]

….

Port ID

SPIA_RX64_CTL_j

SPIA_RX64_SOP_j

SPIA_RX64_EOP_j

j=0,1

ASTOP_ON_EOPj

h01

hff

….

hff

h01

SPIA_RX64_BE_j[7:0]

SPIA_RX64_ERR_j

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