ORSPI4 datasheet(46/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

– Both SPI-4 A and B are enabled

– 32-bit aggregation for all banks

Furthermore, assume the conﬁguration of the SPI-4 is as follows:

– Transmit calendar has 4 ports: 0,1, 2, and 3

– Transmit DPRAMs conﬁgured to 1 partition each

– Transmit PDM assigns burst value of 4 to each port

– Transmit PDM maps port 0 to bank 0, port 1 to bank 1, port 2 to bank 2, and port3 to bank 3

Figure 16 shows how the port polling changes when the link disable for bank 1 is asserted (input signal

SPIB_TX32_LINK_DIS_1 in this conﬁguration). Before SPIB_TX32_LINK_DIS_1 is asserted, the normal port poll-

ing sequence – 0, 1, 2, 3, 0, 1, 2, 3, 0, …. – is seen on the SPIB_TX32_PORT_ID outputs. Each port poll lasts for

the programmed burst value (4 in this example) number of cycles. After the SPIB_TX32_LINK_DIS_1 high transi-

tion, the sequence of port IDs changes to 0, 2, 3, 0, 2, 3, 0, …..

Note that the duration of port 0 is now 6 cycles with port 1 disabled. The 2 extra cycles are needed by the port poll

sequencer to skip over port 1 and continue to port 2. The port poll sequencer does not read data from bank 0 dur-

ing these 2 extra cycles, so they may be considered idle cycles. Before SPIB_TX32_LINK_DIS_1 was asserted,

the port polling period was 4 ports X 4 cycles/port = 16 cycles. After SPIB_TX32_LINK_DIS_1 is asserted, the port

polling period becomes 3 ports X 4 cycles/port + 2 extra cycles = 14 cycles.

Figure 16. Port 1 Disable

Figure 17 shows how the port polling changes when a second bank is disabled.

Here the signal

SPIB_TX32_LINK_DIS_2 is asserted to disable port 2. The port polling period with two ports disabled becomes 2

ports X 4 cycles/port + 4 extra cycles = 12 cycles.

SPIB_TX32_PORT_ID[7:0]

SPIB_TX32_LINK_DIS_3

SPIB_TX32_LINK_DIS_2

SPIB_TX32_LINK_DIS_1

SPIB_TX32_LINK_DIS_0

SPIB_TX32_CLK_0

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