ORSPI4 datasheet(86/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Table 24. Receive Calendar Memory Contents

SPI4 Receive Software Interface

The SPI4 receive interface is conﬁgurable through a System Bus interface incorporated within the embedded core.

The user can gain access to the System Bus either through the integrated MPI interface, or through FPGA

resources using the System Bus Master/Slave interface. Please refer to the appropriate Lattice Semiconductor

data sheets and application notes for more information regarding these interfaces.

The receive SPI4 interface logic incorporates many conﬁgurable control registers, as well as interrupt and status

registers to monitor SPI4 performance. Table 47 provides a memory map and description of each register within

the Transmit portion of the SPI4 embedded core.

Timing Diagrams

As described earlier, there are three main modes of operation - 32-bit mode, 64-bit mode and 128-bit mode. The

timing diagrams described below provide a clear picture of each mode of operation.

For clarity, all timing diagrams are shown for SPIA core. They are identical for the SPIB core. The timing diagram for

a 32-bit read access is shown in Figure 33. A 3-bit read address SPIA_RX32_ADDR_j where j=0,1,2,3 (which is

actually the virtual FIFO partition address) is sent from the FPGA during clock T1. This FIFO address should match

the virtual FIFO address that the user conﬁgured for a given port in the port descriptor memory (PDM). In other

words, the virtual FIFO addressed by this 3-bit address contains the data for the port that was mapped to this buffer

space in the PDM. The read control logic uses this address to generate the internal physical address.

As shown in Figure 33, the user sends SPIA_RX32_RD_j in clock cycle T1. There is a 2-clock latency from the time

the read enable SPIA_RX32_RD_j is asserted to the time read data is presented to the user. Thus, in clock cycle

T3 following SPIA_RX32_RD_j, the embedded core provides the 32-bit data and control. The byte enables

SPIA_RX32_BE_j[3:0] indicate which bytes within the 32-bit word are valid. If the current port ID is different from

the previous port ID, then the ﬁrst data read from the virtual FIFO is the port ID as shown in clock cycle T3. The

SPIA_RX32_CTL_j signal is set to ‘1’ during T3 indicating that read data contains the port ID. The byte enables are

set to “0001” indicating that the least signiﬁcant byte of the 32-bit word contains the port ID. If data is continued to

be read for the same port, then no port ID is presented to the user as this is redundant. The ASTOP_ON_EOPj is

RX Calendar Memory

Address

RX Calendar Memory

Contents (Port ID)

Port Number

0x00

0x01

0x02

0x03

0x04

0x00

0x05

0x01

0x06

0x02

0x07

0x04

0x08

0x00

0x09

0x01

0x0a

0x02

0x0b

0x05

0x0c

0x00

0x0d

0x01

0x0e

0x02

0x0f

0x06

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