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ORCA ORSPI4 Data Sheet

Figure 26. Dummy Write Requirement for MIN_BURST_MODE (32-Bit Mode)

SPI4 FPGA/Embedded Core Timing Delays

When designing application logic within the FPGA to interface with the embedded core, it is important to consider

the input setup and hold time requirements of the embedded core logic. There are two directions for signaling infor-

mation between the FPGA and the embedded core. The ﬁrst is where the FPGA sources transmit data and associ-

ated control signals into the embedded core. Data in this direction is always synchronous to the clock source within

the FPGA. The other data path direction is used to convey Calendar port and status information from the embed-

ded core to the FPGA. All signals in this category are synchronous to the buffered reference clock within the

embedded core. All timing is handled in the

ispLEVER software using frequency preferences on the associated

clocks.

If EOP occurs in any write EXCEPT last

four writes for a given BURST_VAL,

must include 1 dummy write before

terminating writes for the port

Dummy Write:

SPI[A,B]_TX32_ERR_j = 1

SPI[A,B]_TX32_EOP_j = 0

SPI[A,B]_TX32_BE_j(3:0) = 0xF

SPI[A,B]_TX32_DATA = Donít Care

BURST_VAL = n

32-bit

EOP

n-2

If EOP occurs in last four writes as

defined by the BURST_VAL, then no

dummy write is required

DUMMY

WRITE

n-1

EOP

32-bit

EOP

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