ORSPI4 datasheet(61/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 22. Write Synchronization Sequence for 64-Bit Mode

Port 0

Port 1

Port 0

. . .

64-bit Mode (BURST_VAL = 4 example)

1 port duration =

BURST_VAL

clock cycles

End last write no later

than 2 clock cycles before

end of port cycle*

Start 1 st write no sooner than 4

clock cycles before beginning of

initial port cycle*

Port 0,

write 4

. . .

SPI[A,B]_k_CLK_j

SPI[A,B]_k_PORT_ID

* Rules valid for any value of

BURST_VAL in 64-bit mode

Port 0,

write 1

Port 0,

write 2

Port 0,

write 3

. . .

End of data

burst read for

Port 0

Range for Transmit FIFO writes

Minimum separation between repeating

port numbers in Transmit Calendar = 2 for

64-bit mode to allow time to load Transmit

FIFOs for data bursts of any length

Both ports in a minimum separation must

be located in a different bank

Transmit Calendar

Minimum Port Gap

for 64-bit Mode

Port 0

Port 1

Port 0

Set equal

BURST_VAL

for all ports

Conditions for writing to transmit FIFO:

1. If BURST_VAL worth of data is ready to be transmitted

and

2. Port status is not SATISFIED

and

3. Within valid time to load portís transmit FIFO as shown above

then

OK to load transmit FIFO with BURST_VAL of data for that port

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