ORSPI4 datasheet(22/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be

sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast

regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can

be sourced from any I/O pin, PLLs, or the PLC logic.

The improved routing resources offer great ﬂexibility in moving signals to and from the logic core. This ﬂexibility

translates into an improved capability to route designs at the required speeds when the I/O signals have been

locked to speciﬁc pins.

System-Level Features

The Series 4 also provides system-level functionality by means of its microprocessor interface, Embedded System

Bus, quad-port Embedded Block RAMs, universal programmable Phase-Locked Loops, and the addition of highly

tuned networking speciﬁc Phase-Locked Loops. These functional blocks allow for easy, glueless system interfacing

and the capability to adjust to varying conditions in today’s high-speed networking systems.

MicroProcessor Interface

The MPI provides a glueless interface between the FPGA and

PowerPC microprocessors. Programmable in 8-bit,

16-bit,

and 32-bit interfaces with optional parity to the

Motorola

® PowerPC 860 bus, it can be used for conﬁguration

and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4

Embedded System Bus at 66 MHz performance.

A system-level microprocessor interface to the FPGA user-deﬁned logic following conﬁguration, through the system

bus, including access to the Embedded Block RAM and general user-logic, is provided by the MPI. The MPI sup-

ports burst data read and write transfers, allowing short, uneven transmission of data through the interface by

including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2

bytes), or 16-beat (16 x 1 bytes).

System Bus

An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, conﬁguration

logic, FPGA control, and status registers, Embedded Block RAMs, as well as user logic. Utilizing the

AMBA speci-

ﬁcation Rev 2.0 AHB protocol, the Embedded System Bus offers arbiter, decoder, master, and slave elements.

Master and slave elements are also available for the user-logic and a slave interface is used for control and status

of the embedded backplane transceiver portion of the ORSPI4.

The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset func-

tions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is

integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the micro-

processor interface clock, conﬁguration clock (for slave conﬁguration modes), internal oscillator, user clock from

routing, or from the port clock (for JTAG conﬁguration modes).

Phase-Locked Loops

The ORSPI4 provides 4 programmable PLLs accessible through clock routing in the FPGA array. There are two

standard programmable PLLs (PPLL) and 2 high-speed programmable PLLs (HPPLL) available in the ORSPI4.

The two PPLLs are capable of manipulating and conditioning clock outputs from 15 MHz to 200 MHz. The two

HPPLLs are capable of manipulating and conditioning clock outputs from 60 MHz to 420 MHz. Programmable

PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Frequencies can be

adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have differ-

ent multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be

adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available

for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences.

FPGA Conﬁguration

The FPGA functionality is determined by internal conﬁguration RAM. The FPGAs internal initialization/conﬁguration

circuitry loads the conﬁguration data at power-up or under system control. The conﬁguration data can reside exter-

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