ORSPI4 datasheet(21/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional Flip-Flop that

may be used independently or with arithmetic functions.

The PFU is organized in a twin-quad fashion; two sets of four LUTs and FFs that can be controlled independently.

Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may

also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The

carry-out of either mode may be registered in the ninth FF for pipelining.

Each PFU may also be conﬁgured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches)

may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The

FFs also have programmable clock polarity, clock enables, and local set/reset.

The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidi-

rectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional

INVERT to perform

PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU

outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-

world system performance.

Programmable I/O

The Series 4 PIO addresses the demand for the ﬂexibility to select I/Os that meet system interface requirements.

I/Os can be programmed in the same manner as in previous

ORCA devices, with the additional new features which

allow the user the ﬂexibility to select new I/O types that support High-Speed Interfaces.

Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA

array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset,

and global set/reset. On the input side, each PIO contains a programmable latch/Flip-Flop, which enables very fast

latching of data from any pad. The combination provides for very low setup requirements and zero hold times for

signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data sig-

nal, and register the signals without explicitly building a demultiplexer with a PFU.

On the output side of each PIO, an output from the PLC array can be routed to each output Flip-Flop, and logic can

be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals

and other functions of two output signals.

The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to

be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal

can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-

state signal can be registered or nonregistered.

The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These

modes are supported through shift register logic, which divides down incoming data rates, or multiplies up outgoing

data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and

out of the I/O buffers on both edges of the clock.

The new programmable I/O cell allows designers to select I/Os which meet many new communication standards

permitting the device to hook up directly without any external interface translation. They support traditional FPGA

standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-ori-

ented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output lev-

els.

Routing

The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses

with related control signals. Both local and global signals utilize high-speed buffered and non-buffered routes. One

PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide

high connectivity with fast software routing times and high-speed system performance.

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