ORSPI4 datasheet(69/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

These blocks will be described in detail in the following sections. The ORSPI4 Receive functional block diagram is

shown in Figure 29.

Figure 29. ORSPI4 Receive Functional Block Diagram

ORSPI4 Receive Functional Block Overview

The ORSPI4 high-speed receive logic receives high-speed data on 16 LVDS pairs (RDAT[15:0]), control on one

LVDS pair (RCTL) and clock on one LVDS pair (RDCLK) at the SPI4 interface. This is an OIF-SPI-4 02.0 compliant

interface that supports data rates in the range of 622-900 Mbps. Additionally lower-speed data in the range of 100-

200 Mbps is also supported. The high-speed receive interface logic supports both static and dynamic alignment as

speciﬁed by the OIF-SPI-4 02.0 speciﬁcation. Dynamic alignment allows for +/- one bit period of skew. During

dynamic alignment, training patterns are detected and deskew performed. Data is then deserialized into 128-bit

data and 8-bit control bus. The SPI4 receive data protocol logic then extracts the control information such as

PORT_ID, SOP, EOP and ERR into a separate sideband bus while still preserving wire-speed throughput. Data

and control signals are then written into one of four dual-port RAMs (DPRAMs). Per-port buffering is supported for

a maximum of 32 ports. The DPRAMs are built as multiple virtual FIFOs where each FIFO can be allocated for a

port by the user through software. At the FPGA fabric, the user reads data for the desired ports from the FIFOs

[A,B]RSTAT

[A,B]RSCLK

DPRAM

SPI[A,B]_k_DATA_j, BE_j

SPI[A,B]_k_SOPj, EOPj, ERRj

[A,B]STOP_ON_EOPj

SPI[A,B]_k_RD_j

SPI[A,B]_k_ADDR_j

Address

SPI[A,B]_k_CLK_j

Mapper

RDI

[A,B]RDAT

[A,B]RCTL

[A,B]RDCLK

PSS

RSP

RSO

SPI[A,B]_k_STAT

SPI[A,B]_k_PORT_ID

SPI[A,B]_k_EXT_STAT_EN

SPI[A,B]_k_PSS_WE

SPI[A,B]_k_PSS_CLK

RLSTAT

RLSCLK

RDP

data

control

data

control

SPI[A,B]_k_FIFO_EMPTY_j

k = 32, 64 or 128

j= 0, 1, 2 or 3

SPI[A,B]_k_ CTL_j (32 and 64 only)

[A,B]RLSCLK_F

ORSPI4 데이터시트(PDF) 69 Page - Lattice Semiconductor

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