ORSPI4 datasheet(9/263 Pages) LATTICE

9 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 3. ORSPI4 SPI4 Interface Block - Top Level Functional Partitioning

At the embedded core/FPGA interface, data buffering is provided by banks of DPRAM partitioned into FIFOs. FIFO

reads and writes are completely decoupled. Data and accompanying address, packet delineation and error identiﬁ-

cation information are written into the selected FIFO as received - either from the FPGA, in the transmit case, or

from the receive link. For transmit, reads are performed from the FIFOs based on pre-programmed packet format

information, a pre-programmed schedule for link access as read from calendar logic, and far end status information

as received from the transmit status logic. In the receive direction, the receive status logic transmits information

concerning the states of the receive buffers on the receive status links, while the FPGA logic reads data from the

FIFOs as needed under control of the FPGA logic.

The read/write control functions are similar if operating with external RAM. In this case, the internal DPRAM can be

used as clock domain crossing FIFOs.

Formatting/deformatting, ﬂow control processing, and error control logic forms the interface between the DPRAM

banks and the SPI4 transmit and receive blocks. This logic performs the necessary conversions between the SPI4

and FPGA/core interface formats. It also performs DIP-2 (status) and DIP-4 (control) generation/checking. Finally,

the SPI4 interface blocks perform the MUX/DEMUX functions for rate conversion between the internal core data

paths and the SPI4 links and also provides the needed LVDS driver and receiver functions. Either static or dynamic

alignment is available at the receiver interface. Dynamic alignment is used to compensate for bit-to-bit skew at

higher data rates where it becomes difﬁcult to meet tight setup and hold timing requirements.

Input

Protocol

SPI4 Logic - Status

Transmit

Receive

Output

Protocol

SPI4 Logic - Data

Output

Protocol

SPI4 Logic - Status

Input

Protocol

SPI4 Logic - Data

DPRAM

Write

Transmit Buffers

Port

Calendar

Read Control

Control

Banks

Descriptor

Address

Sequencer

Map

Transmit Data

Transmit Status

Transmit Control

FIFO_FULL

32,

TSTAT[1:0]

TSCLK

TDCLK

TDAT[15:0]

TCTL

RSTAT[1:0]

RSCLK

RDCLK

RDAT[15:0]

RCTL

DPRAM

Receive Buffers

Banks

Calendar

Port Status

Sequencer

64,

128

Receive Status

Transmit Buffers

Port

Descriptor

Address

Map

Read Data 128

Read Control

Write

Receive

Control

Center

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