ORSPI4 datasheet(94/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

SPIA_RX128_FIFO_EMPTY ﬂag is ‘1’ and RX_DPRAM_EMPTY_TYPE_SELA[0:3] software register bits in

address 30920 are set to ‘1’, it implies that the FIFO has 15 128-bit words left (1/4 * 64 locations - 1).

As shown in Figure 41, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be

asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until the clock cycle when

EOP is asserted. However, the user is always required to use the ERR signal in conjunction with the EOP signal.

Irrespective of the ERR signal being asserted, the core always transmits the entire packet. Thus, it is relevant for

the user application to sample the ERR signal simultaneously with EOP. Users should also be aware that this is in

asymmetry with the transmit SPI4 core’s behavior. In the transmit direction, user always asserts ERR signal during

an EOP only. Thus, if any loopback is performed from the receive SPI4 (A or B) to the transmit SPI4 (A or B), the

user should ensure that the received ERR signal is not wired directly to the corresponding transmit ERR signal, but

follows the transmit protocol of providing an ERR signal only in the same clock cycle as an EOP and not earlier.

Figure 39. Read Timing with ASTOP_ON_EOP Deasserted - 128-Bit Aggregation Mode

….

FIFO size = 64

SPIA_RX128_CLK

SPIA_RX128_RD

SPIA_RX128_ADDR

Address changed

when penultimate

word is read from FIFO n

SPIA_RX128_EMPTY

FIFO empty

for address p

Indicates

FIFO has 15

words left

SPIA_RX128_DATA

….

Data read 2 cycles after

Address changed to p

2 cycles after

read enable

SPIA_RX128_PORTID

Port ID

SPIA_RX128_SOP

SPIA_RX128_EOP

hffff

….

hffff

SPIA_RX128_BE

SPIA_RX128_ERR

ASTOP_ON_EOP

D63

D62

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