ORSPI4 datasheet(49/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Based upon the trafﬁc characteristics of individual ports and number of ports supported, the user can tailor the

FIFO depth to optimize performance at the FPGA/embedded core interface. When operating in 32-bit mode, four

write cycles are necessary to complete an entire 128-bit line. 64-bit mode requires 2 write accesses, with 128-bit

mode using a single clock per line ﬁll.

When data is read out of the DPRAMs, via the AMA logic, it is read using a 128-bit data bus. Therefore, for each

port serviced, one clock cycle is consumed to read 16 data Bytes and 4 control Bytes from each addressable loca-

tion within a FIFO partition. This corresponds to the SPI4 requirement that only a single SPI4 port's data may exist

on the transmit data bus within any Burst Cycle. A Burst Cycle is made up of 16 Bytes.

Note, for all modes of aggregation, if an entire 128 bits is written to any FIFO partition, with all 16 BE bits deas-

serted, the Quad-word will not be written to the DPRAM, nor will the internal write pointer be incremented for the

selected FIFO partition.

Within the Transmit DPRAM, there are user-programmable ﬁll level thresholds for each enabled partition. The pro-

grammable levels are either 3/4-full or absolutely full. When the ﬁll level of an addressed partition exceeds the pro-

grammed ﬁll level, a FIFO full condition is reported back to the FPGA. Because the ﬁll level operates only on 128

bits, the full ﬂag is only updated after an entire line has been written. The full condition will persist until the FIFO

has been serviced and the ﬁll level drops below the programmed ﬁll threshold.

In order to take a DPRAM temporarily out of service without updating the Calendar, the FPGA can assert the Link

Disable (SPI_TX_LINK_DIS[3:0]) input signal associated with the DPRAM to be disabled. The FPGA is permitted

to continue to write data to the disabled port FIFO, as it will obey all the functionality described above regarding

FIFO ﬁll level and status. When the DPRAM is to be put back into service, the user simply deasserts the LINK_DIS

signal. The associated ports will then be serviced according to the conﬁgured Calendar sequence.

Address Map Arbiter (AMA) Logic Block

The Address Map Arbiter (AMA) logic block is a slave device to the TX Calendar Control logic. Upon receiving a

valid AMA_ID and BURST_VAL vectors, the AMA will attempt to read out data from the indexed DPRAM FIFO par-

tition along with the associated sideband control signals.

In order to take a DPRAM temporarily out of service without updating the Calendar, the FPGA can assert the Link

Disable (SPI_TX_LINK_DIS[3:0]) input signal associated with the DPRAM to be disabled. The FPGA is permitted

to continue to write data to the disabled port FIFO, as it will obey all the functionality described above regarding

DPRAM 3

(Register Bits 6:7) = 00

32-bit data width, partition size 1

32-bit data width, partition size 2

32-bit data width, partition size 4

32-bit data width, partition size 8

64-bit data width, partition size 1

64-bit data width, partition size 2

64-bit data width, partition size 4

64-bit data width, partition size 8

128-bit data width, partition size 1

128-bit data width, partition size 2

128-bit data width, partition size 4

128-bit data width, partition size 8

DPRAM Aggregation

Mode

Address 30903 (SPIA),

30A30 (SPIB)

Virtual FIFO Partition Size

Address 30927 (SPIA),

30A27 (SPIB)

Conﬁguration

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