ORSPI4 datasheet(72/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

SPIA_RX32_ADDR_3[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX32_DATA_3[31:0]

Core

→FPGA FIFO read data.

SPIA_RX32_BE_3[3:0]

Core

→FPGA Byte enables

Bit 3 - Byte enable for SPIA_RX32_DATA_3[31:24]

Bit 2 - Byte enable for SPIA_RX32_DATA_3[23:16]

Bit 1 - Byte enable for SPIA_RX32_DATA_3[15:8]

Bit 0 - Byte enable for SPIA_RX32_DATA_3[7:0]

SPIA_RX32_CTL_3

Core

→FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX32_DATA_3 bus contains

the port ID.

SPIA_RX32_SOP_3

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX32_EOP_3

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX32_ERR_3

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX32_FIFO_EMPTY_3 Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[3]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -1.

ASTOP_ON_EOP3

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX32_CLK_3

FPGA

→ Core FIFO read clock.

SPIA_RX32_RD_3

FPGA

→ Core FIFO read enable.

Status

I/Os

SPIA_RX32_PORT_ID[7:0]

FPGA

→ Core Port ID used by the core as write address into the status RAM.

SPIA_RX32_STAT[1:0]

FPGA

→ Core Port Status corresponding to SPIA_RX32_PORT_ID

SPIA_RX32_EXT_STAT_EN

FPGA

→ Core When set to ‘1’, the status from SPIA_RX32_STAT will be sent on the SPI4

status i/f.

SPIA_RX32_PSS_WE

FPGA

→ Core Write enable to the internal Status RAM.

SPIA_RX32_PSS_CLK

FPGA

→ Core Write clock to the internal Status RAM.

Misc.

I/Os

SPI_DATM_A

FPGA

→ Core Valid only during static data capture. Should be set to ‘0’ in dynamic align-

ment mode.

‘0’ - Bypass delay line circuit on the clock (ARDCLK) path.

‘1’ - Enables delay line circuit on the ARDCLK path.

SPI_DLYTAP_A[2:0]

FPGA

→ Core These bits control the effective delay of the delay line circuit on the ARD-

CLK path. Valid values are from 0-6.

ARLSCLK_F

Core

→FPGA Internal clock (ARDCLK/4) used to clock all receive status logic.

Table 12. SPIA Core Receive FPGA Interface in 32-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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