ORSPI4 datasheet(15/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 4. SERDES Top Level Block Diagram.

The serial channels can each operate at up to 3.7 Gbits/s (2.96 Gbits/s data rate) with a full-duplex synchronous

interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density for the CDR,

byte alignment, and error detection. The core is also capable of frame synchronization and physical link monitoring.

An overview of the individual blocks in the embedded core is presented in the following paragraphs. The SERDES

portion of the core contains a quad transceiver block for serial data transmission at a selectable data rate of 0.6 to

3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks and

high-speed CML interfaces to the serial links.

Serializer and Deserializer (SERDES)

The SERDES portion of the core contains a transceiver block for serial data transmission at a selectable data rate

of 0.6-3.7 Gbits/s. Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core blocks

and high-speed CML interfaces to the serial links.

The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high-

speed (up to 3.7 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each

channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock.

The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbits/s serial data for off-

chip communication. The transmitter generates the necessary clocks from a lower speed reference clock.

The transceiver is controlled and conﬁgured through the system bus in the FPGA logic and through the external 8-

bit microprocessor interface of the FPGA. Each channel has associated dedicated registers that are readable and

writable. There are also global registers for control of common circuitry and functions.

The SERDES performs 8b/10b encoding and decoding for each channel. The 8b/10b transmission code can sup-

port either Ethernet or Fibre Channel speciﬁcations for serial encoding/decoding, special characters, and error

detection.

The user can disable the 8b/10b decoder to receive raw 10-bit words, which will be rate reduced by the SERDES. If

this mode is chosen, the user must also bypass the multichannel alignment FIFOs.

The SERDES macrocell contains its own dedicated PLLs for both transmit and receive clock generation. The user

provides a reference clock of the appropriate frequency. The receiver PLLs extract the clock from the serial input

data and re-time the data with the recovered clock.

MUX/DEMUX Block

The MUX/DEMUX logic converts the data format for the high-speed serial links to a wide, low-speed format for

crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit

SERDES w/

CLOCK/DATA

BYTE-

WIDE

DATA

8b/10b

DECODER/ENCODER

4 FULL-

0.6 Gbits/s

DATA

DUPLEX

SERIAL

CHANNELS

3.7 Gbits/s

0.6 Gbits/s

DATA

3.7 Gbits/s

CML

I/Os

ORCA

SERIES 4

FPGA LOGIC

STANDARD

FPGA I/Os

4:1 MUX/1:4 DEMUX

RECOVERY

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