ORSPI4 datasheet(87/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

set to ‘0’ which means that the core will terminate a 4-word burst when EOP occurs and start transmission of the

next set of data. Note that a new FIFO address ‘p’ is provided during the last 4-word burst of address ‘n’. This

absorbs the 2-clock latency from the time a new address is presented to the DPRAM and the time read data is pre-

sented to the user.

As shown in Figure 34, when the ASTOP_ON_EOPj is asserted, 2 idle clock cycles are inserted after an EOP

occurs. During these idle cycles, the byte enable bits are set to all ‘0’s indicating that the read data is not valid. After

the idle cycles, the core continues to provide read data. The ASTOP_ON_EOPj signal can be asserted anytime

and held high for any length of time during a read data transfer.

At any time, the user can poll for the status of a FIFO within a DPRAM bank by providing just the read address

SPIA_RX32_ADDR_j without providing the read enable. Note that the timing diagram shown in Figure 33 and Fig-

ure 34 indicate a FIFO size of 16 locations. Each location contains four 32-bit data words. Thus when

SPIA_RX32_FIFO_EMPTY_j ﬂag is ‘1’ and RX_DPRAM_EMPTY_TYPE_SELA[j] software register bit in address

30920 is set to ‘1’, it implies that the FIFO has three 4-word data left (1/4 * 16 locations - 1).

As shown in Figure 35, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be

asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until EOP occurs. However,

the user is always required to use the ERR signal in conjunction with the EOP signal. Irrespective of the ERR signal

being asserted, the core always transmits the entire packet. Thus, it is relevant for the user application to sample

the ERR signal simultaneously with EOP. Users should also be aware that this is in asymmetry with the transmit

SPI4 core’s behavior. In the transmit direction, user always asserts ERR signal during an EOP only. Thus, if any

loopback is performed from the receive SPI4 (A or B) to the transmit SPI4 (A or B), the user should ensure that the

received ERR signal is not wired directly to the corresponding transmit ERR signal, but follows the transmit protocol

of providing an ERR signal only in the same clock cycle as an EOP and not earlier.

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