ORSPI4 datasheet(82/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

by the calendar. This ensures that the bandwidth allocated for a given port is maintained and the port’s FIFO is

emptied at the same rate that it is being ﬁlled up at the far-end transmitter. For example, if the calendar assumes

that the buffer for port 2 is ﬁlled more frequently than the buffer for port 4, then the FPGA logic must read the buffer

(virtual FIFO) for port 2 more frequently than port 4 to ensure that bandwidth requested for port 2 is maintained

across the SPI4 link. The user also has a choice to not use the per-port buffers and treat the DPRAMs as pure

clock-domain crossing FIFOs. This is done by simply conﬁguring each DPRAM in 128-bit mode and setting up the

number of virtual FIFO partitions to “1”.

If the user application supports more than 32 ports, multiple ports need to share a buffer or external memory can

be used. The ORSPI4 core provides a QDR-II SRAM Memory Controller for additional buffering. The QDR-II SRAM

memory was chosen owing to the wire-speed throughput that can be realized through dedicated write and read

ports. In this case, the user must implement control logic to sequence external memory reads from the selected vir-

tual FIFOs and the FIFOs are used only for crossing between clock domains. In many cases a second QDR-II

memory interface is needed, thus a soft IP version of the core is available.

Suppose there are 6 ports, and each port is mapped to a single buffer or virtual FIFO:

• The ﬁrst step is to decide the aggregation mode and FIFO size depending on the bandwidth needed by the

port(s). This is shown in Table 19.

• The second step is to conﬁgure the DPRAMs through software register settings shown in Table 20. Note that

DPRAM banks 2 and 3 are conﬁgured identically since they are conﬁgured to be a 64-bit interface.

• The last step is to conﬁgure the PDM using the procedure described in the Address Mapper section. The con-

tents of the PDM are shown in Table 21.

Table 19. DPRAM Conﬁguration Example

Table 20. DPRAM Software Register Settings Example

Table 21. PDM Contents Example

DPRAM bank

Aggregation

Mode

Number of

Virtual FIFOs

Virtual FIFO

Size (bytes)

32-bit

2,3

64-bit

DPRAM Bank

Aggregation Mode

Number of Virtual FIFOs

RX_DPRAM_0_AGGR_MODE = 00

RX_DPRAM_0_NUMFIFO = 01

RX_DPRAM_1_AGGR_MODE = 00

RX_DPRAM_0_NUMFIFO = 01

RX_DPRAM_2_AGGR_MODE = 01

RX_DPRAM_0_NUMFIFO = 01

RX_DPRAM_3_AGGR_MODE = 01

RX_DPRAM_0_NUMFIFO = 01

Port ID

Bank ID

Partition Address

0x00

000

0x01

001

0x02

000

0x03

001

0x04

000

0x05

001

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