ORSPI4 datasheet(2/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

High-Speed ORCA Series 4 FPGA

■ Internal performance of > 250 MHz

■ Over 16K programmable logic elements

■ 1.5V operation (30% less power than 1.8 V operation)

■ Comprehensive I/O selections including LVTTL, LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT,

DDR, LVDS, bused-LVDS, and LVPECL

■ 1036-pin ftSBGA package provides enough FPGA user I/Os (498) for 4 full-duplex XGMII interfaces, 4

full-duplex PL-3 interfaces, etc; a 40% smaller 1156-pin fpBGA package is available with 356 FPGA user

I/Os

Introduction

The SPI4 blocks provide dual 10 Gbits/s physical-to-link layer interfaces in conformance to the OIF-SPI4-02.0

speciﬁcation. Each block provides a full-duplex interface with an aggregate bandwidth of 13.6 Gbits/s. This is

achieved by using 16 LVDS pairs each for RX and TX operating at a maximum data rate of 900 Mbits/s with a 450

MHz DDR clock. Both static and dynamic alignment are supported at the receive interface. Dynamic alignment is

used to compensate for bit-to-bit skew at higher data rates, where it becomes difﬁcult to meet tight setup/hold

requirements. DIP-4 and DIP-2 parity generation and checking are supported. Data buffering of 8K bytes for both

transmit and receive is provided by embedded Dual-Port RAM in each SPI4 core. Internal 1K deep main and

shadow calendar supports scheduling of up to 256 ports. The Transmit and Receive Status FIFOs can also store

ﬂow control information for up to 256 ports, the maximum speciﬁed in the SPI4 speciﬁcation.

An independent QDRII Memory Controller block provides data buffering between the FPGA logic and external

memory and supports a throughput of greater than 20 Gbits/s. Data is transferred to and from memory through two

sets of 36-bit unidirectional data lines operating at up to 175 MHz DDR. A set of 72 data signals is available to

transfer data across the core-FPGA interface and allows the system to utilize the bandwidth available with second-

generation Quad Data Rate (QDRII) SRAMs. Of the 72 data signals, 8 signals can be either used for parity or data.

A soft IP version of this core is also available to allow a second data buffer on this device.

The High-Speed SERDES block supports four serial links, each operating at up to 3.7 Gbits/s (2.96 Gbits/s data

rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in RX Clock

and Data Recovery (CDR) and transmitter preemphasis. The SERDES block is identical to that in the ORT82G5

FPSC, supports embedded 8b/10b encoding/decoding and implements link state machines for both 10G Ethernet,

and 1G/2G/10G Fibre Channel. The state machines are IEEE P802.3ae/D4.01 XAUI based and also support FC

(ANSI X3.230:1994) link synchronization.

Table 1. ORCA ORSPI4 — Available FPGA Logic

Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate

ranges are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40%

EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR

usage and 4 PLL's.

The ORSPI4 device is offered in two packages: 1036 ftSBGA and 1156 fpBGA. The 1036 package offers 498 FPGA User I/Os while the 1156

package offers 356 FPGA User I/Os. Additionally, the SERDES option is not available on the 1156 package.

Device

PFU Rows

PFU

Columns

Total PFUs

FPGA Max

User I/O

LUTs

EBR

Blocks

EBR Bits

(K)

Usable*

Gates (K)

ORSPI4

2,024

498/356

16,192

148

471-899

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