ORSPI4 datasheet(14/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Memory Controller - Overview

The Memory Controller block controls an interface to external Quad Data Rate (QDRII) SRAM for data buffering

between the FPGA logic and external memory. The key features of the Memory Controller interface are described

below:

Memory Controller Features

• Independent Memory Controller interface to external Quad Data Rate (QDRII) SRAMs from multiple suppliers for

data buffering.

– Provides additional packet buffering for > 32 ports

– Provides trafﬁc smoothing for any number of ports

• The Controller supports a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 inter-

face at 10 Gbits/s can be buffered.

• The QDRII SRAM supports this throughput with 36 unidirectional data lines in both the read and write directions.

• The controller block provides the ability to access external QDRII SRAM through the FPGA.

– A set of 72 data signals across the core-FPGA interface

– Of the 72, 8 signals can be either used for parity or data.

– Simple asynchronous FIFO interface to FPGA for ease of design. A high-speed clock signal is provided to

the FPGA as an option to make the write and read synchronous, if desired.

• The core passes the data transparently to and from the QDRII SRAM in two-word or four-word bursts. Interfaces

to memory are 36 bits wide and the address buses are 18 bits wide.

– Supports the interfaces required for a 512K x 36 bit (18 Mbit) QDRII SRAM in two-word burst mode.

– Only 17 address lines are required in four-word burst mode.

• Status/Alarm reported to user through registers

– Data length mismatch from the write controller state machine

– Data instruction coherency error

– Write data, Read data FIFO overrun and underrun errors

• Additional high-speed Memory Controller can be implemented in FPGA gates if required.

SERDES Logic Block - Overview

The SERDES logic block in of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and four Seri-

alizer/Deserializer (SERDES) macrocells to support four channels of 8b/10b (

IEEE 802.3.2002) encoded serial

links. The logic block also contains Fiber Channel and XAUI-based state machines, logic to support multi-channel

alignment and MUX/DEMUX logic for the FPGA/core interface. Figure 4 shows the SERDES top level block dia-

gram and the basic data ﬂow. Boundary scan for the SERDES only includes programmable I/Os and does not

include any of the embedded block I/Os.

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