ORSPI4 datasheet(6/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Embedded Core Overview - Functions and Features

The embedded core contains four separate functional blocks, two SPI4 interface blocks, a high-speed Memory

Controller block, and a quad SERDES block providing 4 channels of 0.6-3.7 Gbits/s SERDES. Features common to

all blocks include:

• Improved

PowerPC

® 860 and PowerPC II high-speed synchronous MicroProcessor Interface that can be used

for conﬁguration, readback, device control, and device status; as well as for a general-purpose interface to the

FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous

PowerPC processors

with user-conﬁgurable address space provided.

• New embedded

AMBA ™ speciﬁcation 2.0 AHB system bus (ARM

® processor) facilitates communication among

the MicroProcessor Interface, conﬁguration logic, and embedded core blocks.

• FPSC Design Kit available for use with

ispLEVER development system software. Supported by industry-stan-

dard CAE tools for design entry, synthesis, simulation, and timing analysis.

SPI4 Interface Blocks - Overview

The ORSPI4 FPSC provides two independent SPI4 interface blocks in the embedded core. The two SPI4 blocks

are identical and the following overview applies to both blocks. In the following sections, the SPI4 protocol conven-

tions for “transmit” and “receive” are not followed, since in various applications the ORSPI4 FPSC could be used to

perform different functions at various levels in the SPI4 protocol stack. Instead, the “transmit” functions are those

used to transmit data to and receive current status information from the device at the other end of the SPI4 link.

The “receive” functions are those used to receive data from and transmit current status information to the device at

the other end of the SPI4 link.

Each SPI4 block supports a standard 10 Gbits/s physical-to-link layer interface in conformance to the speciﬁcation.

This is achieved by using 16 LVDS pairs each for RX and TX that operate at a maximum data rate of 900 Mbits/s

with a 450 MHz DDR clock. Data buffering of 8 Kbytes each in the transmit and receive direction (example: 256

bytes each for up to 32 ports) is provided by embedded Dual-Port RAM (DPRAM). Aggregation of buffer space is

supported for systems with less than 32 ports. The internal calendar and Transmit and Receive Status FIFOs have

been sized so that applications with larger numbers of ports can be supported. The ORSPI4 has been designed to

support up to 256 ports, the maximum speciﬁed in the SPI4 speciﬁcation.

Despite operating independently, both the transmit path and the receive path logic perform similar functions and

the partitioning of both logical blocks are quite similar as shown in Figure 3. The top level partitioning is between

the logic blocks to transfer and process data and control information, and the logic blocks to generate, transfer and

process status information.

SPI4 Interface Block Features

• Each SPI4 block provides a standard 10 Gbits/s physical-to-link layer interface in conformance to the OIF-SPI4-

02.0 speciﬁcation. Each interface provides an aggregate bandwidth of 13.6 Gbits/s. This is achieved by using 16

LVDS pairs each for RX and TX with a maximum data rate of 900 Mbits/s using a 450 MHz DDR clock.

• The blocks can be used for applications such as interconnecting an OC-192 framer with a proprietary packetized

interface, to a network processor with a SPI4 based packet interface or vice versa.

• Support for “static” or “dynamic” alignment at the receive interface. At clock rates above 350 MHz DDR, it

becomes difﬁcult to meet the tight setup/hold requirements at the receiver using static alignment. In this case,

dynamic alignment is used to compensate for bit-to-bit skew.

• Dynamic alignment automatically compensates for Process, Voltage, and Temperature (PVT) changes in devices

and systems.

– Full bandwidth up to 450 MHz DDR (900 Mbits/s throughput)

– Dynamically performs alignment based on 16 phases of the RX clock for improved accuracy

– Alignment algorithm can be done based on excessive bit errors on the DIP-4 calculation

– Clock skews up to +/- one clock cycle can be compensated by the dynamic alignment logic

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