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ORSPI4 데이터시트(PDF) 102 Page - Lattice Semiconductor

부품명 ORSPI4
상세설명  Dual SPI4 Interface and High-Speed SERDES FPSC
PDF  263 Pages
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제조업체  LATTICE [Lattice Semiconductor]
홈페이지  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ORSPI4 데이터시트(HTML) 102 Page - Lattice Semiconductor

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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
102
Receive Clocking
The following descriptions and figures show the SPIA core. The SPIB core is identical.
Figure 46. SPI4 RX Clocking
ARDCLK[P,N]: SPI4 line clocks received with data and control. These are external LVDS input pads.
SPIA_RXk_CLK_j: Read clocks to each of the four asynchronous DPRAMs.
ARLSCLK_F: Output clock from receive status logic to FPGA.
SPIA_RXk_PSS_CLK: Write clocks from FPGA to the receive status RAM. The ARLSCLK_F clock can be used to
source this clock as shown by dotted lines in the figure.
ARSCLK[P,N]: LVDS receive status outputs. External pads.
RSCLKA: 3.3 V LVTTL receive status output. External pads.
SPIA RX Status
SPIA RX Core
(Data)
FPGA
SPIA_RXk_CLK_0
SPIA_RXk_CLK_1
SPIA_RXk_CLK_2
SPIA_RXk_CLK_3
ARLSCLK_F
k = 32, 64, or 128
ARDCLKP
ARDCLKN
ARSCLKP
ARSCLKN
RSCLKA
LVTTL Input
LVDS Output
j =0, 1, 2 or 3
SPIA_RXk_PSS_CLK



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