ORSPI4 datasheet(108/263 Pages) LATTICE

108 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

108

Figure 49. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)

SERDES/FPGA Logic Interface and 4:1 Multiplexer

These blocks provide the data formatting and transmit data and clock signal transfers between the SERDES and

the FPGA Logic. Control and status registers in the FPGA portion of the chip control the transmit logic and record

status. These bits are passed to the core using the FPGA System Bus and are described in later sections of this

data sheet.

The low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. The

data bytes are conveyed to the MUX via the TWDx[31:0] ports (where x represents the channel label [A,B,C or D].

The control bits are TCOMMAx[3:0] which deﬁne whether the input byte is to be interpreted as data or as a special

character and TBIT9x[3:0] which are used to force a negative disparity present state. The data and control signals

are synchronized to the transmit clock, TSYS_CLK_x. Both the data and control are strobed into the core on the

rising edge of TSYS_CLK_x. Note that each TBIT9x[3:0] controls the disparity of the encoded version of its corre-

sponding data byte. Setting bit TBIT9C[3] to “1”, for instance, will force the 8b/10b encoder to asserts a current neg-

ative running disparity state. This will cause it to encode TWDC[31:24] positively (more “1”'s than “0”'s). Setting

TBIT9x to 0 will leave the encoder free to alternate between positive and negative encoding to maintain a zero run-

ning disparity.

The MUX is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to

10 bits of data/control at the SERDES transmit interface. The MUX has two clock domains - one based on the clock

received from the SERDES block and a second that comes from the FPGA at 1/4 the frequency of the SERDES

clock. The time sequence of interleaving data/control values is shown in Figure 50.

÷ 4

FIFO

4:1 MUX

(x9)

PLL

PRBS

Gen.

CML

Buffer

with Pre-

emphasis

10:1

MUX

8B/10B

Encoder

(with

bypass)

Interface and MUX Block

TX SERDES Block

STBD_x[7:0]

STBD_x[8]

STBD_x[9]

STBC311_x

8-bit data

K-control

Force-ve disparity

312.5 MHz

HDOUTP_x

HDOUTN_x

REFCLKP

REFCLKN

CML

Buffer

Backplane

Serial

Link

FPGA

Logic

TWDx[31:0]

TCOMMAx[3:0]

TBIT9x[3:0]

TSYS_CLK_x

MUX

TCK78

78.125 MHz

TCKSEL[0:1]

Logic Common to Quad

From other 3

channels

To other 3

channels

From Control

{

Note: x= [A, B, ... D]

156.25 MHz

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