ORSPI4 datasheet(156/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

156

Table 45. ORSPI4 Memory Space

Table 46. Top-level Interrupt Status Register 30B29

Table 47 details the memory map for the FPSC portion of the ORSPI4 device.

Addresses for the control registers for the FPGA portion of the device are detailed in the ORCA Series 4 datasheet.

This table shows the databus oriented for the PPC interface. DB0 is the MSB, while DB7 is the LSB. If the user

master interface is used to perform operations to the ASIC core then the databus must be used in the opposite

notation, where DB7 is the MSB and DB0 is the LSB.

Address (Hex)

Description

3000x

Channel A in SERDES, internal registers

3001x

Channel B in SERDES, internal registers

3002x

Channel C in SERDES, internal registers

3003x

Channel D in SERDES, internal registers

308xx

Channel registers outside the SERDES

3090x - 3092x

SPI4 Core A Control registers

30930 - 3094x

SPI4 Core A Status registers

30950 - 3097x

SPI4 Core B Control registers

30980 - 3099x

SPI4 Core B Status registers

31000 - 317FF

SPI4 Core A/B conﬁgurable RAM address space

30100 - 3010F

Memory Controller registers

BIT

Interrupt Source

Associated Registers

SERDES

3000, 3010, 3020, 3030

Memory Controller

30B09

Memory Controller

30B08

DPRAM

SPIA (3090C-3090F, 30918-3091B, 30928-3092F)

SPIB (30A0C-3090F, 30A18-30A1B, 30A28-30A2F)

SPI_B_2

30A1C

SPI_B_1

30A1D

SPI_A_2

3091C

SPI_A_1

3091D

Table 47. Memory Map

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

SERDES Alarm Registers (Read Only), x = [A, ...,D]

30000

30010

30020

30030

[0]

Reserved

[1]

LKI_x

Receive PLL Lock Indication, Channel x. LKI_x = “1” indicates the receive

PLL is locked.

[2:7]

Reserved

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