ORSPI4 datasheet(262/263 Pages) LATTICE

262 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

262

Table 93. Pb-free Industrial Ordering Information

Revision History

Device Family

Part Number

Speed

Grade

Package Type

Ball Count

Grade

ORSPI4

ORSPI4-2FN1156I

Pb-free fpBGA

1156

ORSPI4-1FN1156I

1. For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commer-

cial speed grade -3XXXXXC is also marked with the industrial grade -2XXXXXI. The commercial grade is always one speed

grade faster than the associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial

grade only.

2. Convert to FTE package per PCN#16A-07.

Date

Version

Change Summary

–

Previous Lattice releases.

July 2004

02.0

Phase-Locked Loops description has been updated.

ORSPI Transmit FPGA/Embedded Core Interface description has been updated.

SPIA Core Transmit FPGA Interface in 32-Bit Mode.

SPIA Core Transmit FPGA Interface in 64-Bit Mode, and Table 4. SPIA Core Transmit

FPGA Interface in 128-Bit Mode have been updated.

Link Disable section has been updated.

TX DPRAM section has been updated.

Port Credit Field Update Flow Chart has been added and the description has been

updated.

Calendar Programming section has been updated to "After programming the calendar

memory, the TX_CAL_MEM_SEL bit is set to '0'."

SPIA Core Receive FPGA Interface in 32-Bit Mode has been updated.

RDI Block description has been updated.

Far End Loopback Setup section has been added.

ORSPI4 QDRII Memory Controller Block Diagram has been updated.

FPGA/Embedded Core Signals has been updated.

ORSPI4 Memory Controller Interface to FPGA - Write Timing Diagram has been updated.

ORSPI4 Memory Controller Interface to QDRII: 4-Word Burst Mode has been updated.

ORSPI4 Memory Controller Interface to FPGA - Read Timing Diagram has been updated.

Memory Controller Instruction Latency section has been updated.

Memory Map has been updated.

ORSPI4 Post conﬁguration Standby Current has been added.

ORSPI4 SERDES Worst Case Power Table has been updated with footnote 2.

Supported Data Rates has been updated.

SPI4.2 Data Interface has been added."

Timing Reference Points with Respect to Clock Edge has been updated.

Data Path Interface Timing for Static Alignment has been updated.

Status Path Interface OIF-SPI4-02.2 Speciﬁcation Timing (Reference) has been updated.

Status Path Interface ORSPI4 Timing in Centered (OIF) Mode has been updated.

Status Channel Reference Points with Respect to Clock Edge has been updated.

Status Path Interface ORSPI4 Timing in Legacy Mode has been updated.

Channel Output Jitter (3.125 Gbits/s) has been updated.

Channel Output Jitter (2.5 Gbits/s) has been updated."

Memory Controller Input/Output Timing Speciﬁcation has been added.

Memory Controller Output Timing Speciﬁcation has been added.

Memory Controller Input Timing Speciﬁcation has been added.

ORSPI4 데이터시트(PDF) 262 Page - Lattice Semiconductor

ORSPI4 데이터시트(HTML) 262 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL