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ORSPI4 데이터시트(PDF) 115 Page - Lattice Semiconductor

부품명 ORSPI4
상세설명  Dual SPI4 Interface and High-Speed SERDES FPSC
PDF  263 Pages
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제조업체  LATTICE [Lattice Semiconductor]
홈페이지  http://www.latticesemi.com
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ORSPI4 데이터시트(HTML) 115 Page - Lattice Semiconductor

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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
115
ground state and start its search for the idle ordered sets again. A typical valid sequence for achieving link synchro-
nization would be K28.5 D21.4 D21.5 D21.5 repeated three times.
In the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of
code violation that might result due to running disparity errors. If it were to receive four such consecutive invalid
words, the link machine loses its synchronization and once again enters the loss of synchronization state (LOS). A
pair of valid words received by the machine overcomes the effect of a previously encountered code violation. LOS
is indicated by the status of WDSYNC_x output which now transitions from “1” to “0”. LOS is also indicated by
DEMUXWAS_x status register bit. This bit is set to “0” during loss of synchronization. At this point the machine
attempts to establish the link yet again. Figure 55 shows the state diagram for the Fibre Channel link state
machine.
Figure 55. Fibre Channel Link State Machine State Diagram
XAUI Link Synchronization Function
For each lane, the receive section of the XAUI link state machine incorporates a synchronization state machine that
monitors the status of the 10-bit alignment. A 10-bit alignment is done in the SERDES based on a comma charac-
ter such as K28.5. A comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that can-
not appear across the boundary between any two valid 10-bit code-groups. This property makes the comma useful
for delimiting code-groups in a serial stream. This mechanism incorporates a hysteresis to prevent false synchroni-
zation and loss of synchronization due to infrequent bit errors. For each lane, the sync_complete signal is disabled
until the lane achieves synchronization. The synchronization state diagram is shown in Figure 56. The XAUI state
machine does not have any control over the SERDES byte aligner. It is the user’s responsibility to control the byte
aligner through software access of register map address 30800.
LOS = 1
LAST ORDERED SET RECEIVED:
VW
RST
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1)
OS
CV
OS
OS
OS
CV
CV
CV
CV
CV
1VW
1VW
1VW
2 VW
2 VW
2 VW
a
b
c
d
e
h
g
f
LOSS OF SYNCHRONIZATION (WDSYNC_X = 0)
LSM_ENABLE
+
POWERUP_RESET
VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION) WITH AT LEAST
CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION)
OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER)
1VW: FIRST VALID WORD AFTER A CODE VIOLATION
TWO PRECEEDING VALID WORDS
2VW: SECOND VALID WORD AFTER A CODE VIOLATION



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