ORSPI4 datasheet(117/263 Pages) LATTICE

117 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

117

Figure 56. XAUI Link Synchronization State Diagram

Reference Clock Requirements

There is one pair of SERDES reference clock inputs on the ORSPI4. The differential reference clock is distributed

to all channels in the block. Each channel has a differential buffer to isolate the clock from the other channels. The

input clock is preferably a differential signal; however, the device can operate with a single-ended input. The input

reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jitter compo-

Loss_of_Sync

sync_status <=FAIL

enable_CDET <= TRUE

sync_complete

reset

Comma_Detect_1

enable_CDET <= FALSE

cg_bad

cg_comma

cg_bad

Comma_Detect_2

Comma_Detect_3

cg_comma

Sync_Aqc’d_1

Sync_Aqc’d_1a

sync_status <= OK

no_comma and cg_bad

sync_status <= OK_NOC

cg_bad

cg_comma

Sync_Aqc’d_2

Sync_Aqc’d_3

Sync_Aqc’d_4

Sync_Aqc’d_2a

Sync_Aqc’d_3a

Sync_Aqc’d_4a

gd_cg <= gd_cg + 1

gd_cg <= 0

cg_good

cg_good x

(gd_cg ! = 3)

cg_bad

cg_good x (gd_cg = 3)

cg_good x

(gd_cg ! = 3)

cg_bad

cg_good*(gd_cg=3)

cg_good

cg_bad

cg_good x (gd_cg = 3)

cg_good

cg_good x

(gd_cg ! = 3)

cg_bad

gd_cg <= 0

gd_cg <=gd_cg + 1

no_comma and cg_bad

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