| 전자부품 데이터시트 검색엔진 |
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ORSPI4 데이터시트(PDF) 187 Page - Lattice Semiconductor |
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ORSPI4 데이터시트(HTML) 187 Page - Lattice Semiconductor |
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187 / 263 page ![]() Lattice Semiconductor ORCA ORSPI4 Data Sheet 187 Input Eye-Mask Characterization Figure 97 provides an eye-mask characterization of the SERDES receiver input. The eye-mask is specified below for two different eye-mask heights. It provides guidance on a number of input parameters, including signal ampli- tude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental character- istics of transmit signal and the interconnection link design result in eye-closure. This, combined with the eye- opening limitations of the line receiver, can provide a good indication of a link’s ability to transfer data error-free. The Clock and Data Recovery (CDR) portion of the ORSPI4 SERDES receiver has the ability to filter incoming sig- nal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask specifications of Table 70 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition. When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is significantly better. For this case error-free data detection can occur even with a completely closed eye-mask. Figure 97. Receive Data Eye-Diagram Template (Differential) Table 70. Receiver Eye-Mask Specifications1 Parameter Conditions Value Unit Input Data Eye Opening Width (H) @ 3.125 Gbps V=175 mV diff 1 0.55 UIP-P Eye Opening Width (T) @ 3.125 Gbps V=175 mV diff 1 0.15 UIP-P Eye Opening Width (H) @ 3.125 Gbps V=600 mV diff 1 0.35 UIP-P Eye Opening Width (T) @ 3.125 Gbps V=600 mV diff 1 0.10 UIP-P Eye Opening Width (H) @ 2.5 Gbps V=175 mV diff 1 0.42 UIP-P Eye Opening Width (T) @ 2.5 Gbps V=175 mV diff 1 0.15 UIP-P Eye Opening Width (H) @ 2.5 Gbps V=600 mV diff 1 0.33 UIP-P Eye Opening Width (T) @ 2.5 Gbps V=600 mV diff 1 0.10 UIP-P 1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0 oC to 85oC, 1.425 V to 1.575 V supply. H V 1.2 V UI T |
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