ORSPI4 datasheet(183/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

183

Table 63. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode

Note: This table compares the OIF Speciﬁcation requirements vs. the ORSPI4 Speciﬁcation. There is no OIF Speciﬁcation for LVDS buffers.

Figure 95. ORSPI4 Static Mode Status Signals Data Capture (Reference Point D)

OIF-SPI4-02.0

Speciﬁcation

Requirements

ORSPI4 Timing in

Centered (OIF) Mode

Symbol

Description

Min

Max

Min

Max

Units

TDCLK/RDCLK frequency

—

450

—

450

MHz

TSCLK/RSCLK frequency

—

112.5

—

112.5

MHz

—

TSCLK/RSCLK duty cycle

tdia

RSTAT invalid with respect to clock edge

(Reference point C)

—

2.5

—

0.30

tdib

RSTAT invalid with respect to clock edge

(Reference point C)

—

1.0

—

0.45

Setup time for TSTAT with respect to TSCLK -

LVTTL Buffers (Reference point D)

2.0

—

1.0

—

Setup time for TSTAT with respect to TSCLK -

LVDS Buffers (Reference point D)

—

1.0

—

Hold time for TSTAT with respect to TSCLK -

LVTTL Buffers (Reference point D)

0.5

—

0.5

—

Hold time for TSTAT with respect to TSCLK -

LVDS Buffers (Reference point D)

—

0.7

—

Reference Point D

TSTAT/

RSTAT

LVTTL

LVDS

STATUS_IO_SEL

TSCLK/

RSCLK

LVTTL

LVDS

SPI_STAM

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