MPC8321EVRADDC datasheet(21/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet and MII Management

Figure 7 shows the MII transmit AC timing diagram.

Figure 7. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC Timing Specifications

Table 24 provides the MII receive AC timing specifications.

TX_CLK data clock fall time

tMTXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 24. MII Receive AC Timing Specifications

At recommended operating conditions with OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typical

Max

Unit

RX_CLK clock period 10 Mbps

tMRX

—400

—

RX_CLK clock period 100 Mbps

tMRX

—40

—

RX_CLK duty cycle

tMRXH/tMRX

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

tMRDXKH

10.0

—

RX_CLK clock rise time

tMRXR

1.0

—

4.0

Table 23. MII Transmit AC Timing Specifications (continued)

At recommended operating conditions with OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typical

Max

Unit

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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