 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
MPC8321EVRADDC 데이터시트(PDF) 64 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8321EVRADDC 데이터시트(HTML) 64 Page - Freescale Semiconductor, Inc |
|
|
64 / 82 page  MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 64 Freescale Semiconductor Clocking 22 Clocking Figure 43 shows the internal distribution of clocks within the MPC8323E. Figure 43. MPC8323E Clock Subsystem The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode, respectively. Core PLL System LBC LCLK[0:1] core_clk e300c2 core csb_clk to rest CLKIN csb_clk Local Bus PCI_CLK_OUT[0:2] PCI_SYNC_OUT PCI_CLK/ Clock Unit of the device lbc_clk PCI Clock PCI_SYNC_IN Memory Device /n to local bus Clock Divider ( ÷2) 3 MEMC_MCK MEMC_MCK DDR ddr_clk DDR Memory Device PLL to DDR memory controller Clock CFG_CLKIN_DIV /2 Divider Divider 1 0 QUICC PLL Engine ce_clk to QUICC Engine block MPC8323E Crystal CLKIN |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
