MPC8321EVRADDC datasheet(80/82 Pages) FREESCALE

80 / 82 page

MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Document Revision History

25.2

Part Marking

Parts are marked as in the example shown in Figure 46.

Figure 46. Freescale Part Marking for PBGA Devices

26 Document Revision History

Table 67 provides a revision history for this hardware specification.

Table 67. Document Revision History

Rev.

No.

Date

Substantive Change(s)

09/2010

• Replaced all instances of “LCCR” with “LCRR” throughout.

• Added footnotes 3 and 4 in Table 2, “Recommended Operating Conditions3.”

• Modified Section 8.1.1, “DC Electrical Characteristics.”

• Modified Table 23, “MII Transmit AC Timing Specifications.”

• Modified Table 24, “MII Receive AC Timing Specifications.”

• Added footnote 7 and 8, and modified some signal names in Table 55, ”MPC8323E PBGA Pinout

Listing.”

12/2009

• Removed references for note 4 from Table 1.

• Added Figure 2 in Section 2.1.2, “Power Supply Voltage Specification.

• Added symbol TA in Table 2.

• Added footnote 2 in Table 2.

• Added a note in Section 4, “Clock Input Timing for rise/fall time of QE input pins.

• Modified CLKIN, PCI_CLK rise/fall time parameters in Table 8. Modified min value of tMCK in Table 19.

• Modified Figure 43.

• Modified formula for ce_clk calculation in Section 22.3, “System Clock Domains.

• Added a note in Section 22.4, “System PLL Configuration.

• Removed the signal ECID_TMODE_IN from Table 55.

• Removed all references of RST signals from Table 55.

MPCnnnnetppaaar

core/platform MHZ

ATWLYYWW

CCCCC

PBGA

*MMMMM

YWWLAZ

Notes:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

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