MPC8321EVRADDC datasheet(11/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

RESET Initialization

4.2

AC Electrical Characteristics

The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending

on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the MPC8323E.

RESET Initialization

This section describes the AC electrical specifications for the reset initialization timing requirements of

the MPC8323E. Table 9 provides the reset initialization AC timing specifications for the reset

component(s).

CLKIN input current

0 V

≤ VIN ≤ OVDD

IIN

—±5

μA

PCI_SYNC_IN input current

0 V

≤ VIN ≤ 0.5 V or

OVDD – 0.5 V ≤ VIN ≤ OVDD

IIN

—±5

μA

PCI_SYNC_IN input current

0.5 V

≤ VIN ≤ OVDD – 0.5 V

IIN

—±50

μA

Table 8. CLKIN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

CLKIN/PCI_CLK frequency

fCLKIN

—

66.67

MHz

CLKIN/PCI_CLK cycle time

tCLKIN

—

CLKIN rise and fall time

tKH, tKL

0.6

0.8

PCI_CLK rise and fall time

tPCH, tPCL

0.6

0.8

1.2

CLKIN/PCI_CLK duty cycle

tKHK/tCLKIN

—

CLKIN/PCI_CLK jitter

—

±150

4, 5

Notes:

1. Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum

operating frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

Table 9. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset

flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock applied to CLKIN

when the MPC8323E is in PCI host mode

—

tCLKIN

Required assertion time of PORESET with stable clock applied to

PCI_SYNC_IN when the MPC8323E is in PCI agent mode

—

tPCI_SYNC_IN

Table 7. CLKIN DC Electrical Characteristics (continued)

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