MPC8321EVRADDC datasheet(63/82 Pages) FREESCALE

63 / 82 page

MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Package and Pin Listings

VDD

K10, K11, K12, K13, K14, K15,

K16, K17, L10, L17, M10, M17,

N10, N17, P10, P17, R10, R17,

T10, T17, U10, U11, U12, U13,

U14, U15, U16, U17

VDD

——

VSS

B23, E7, E11, E13, E17, E21,

F11, F13, F17, F21, F23, G5,

H22, K5, K6, L11, L12, L13,

L14, L15, L16, L21, M11, M12,

M13, M14, M15, M16, N6, N11,

N12, N13, N14, N15, N16, P5,

P11, P12, P13, P14, P15, P16,

P21, R11, R12, R13, R14, R15,

R16, R22, T6, T11, T12, T13,

T14, T15, T16, U5, U21, V23,

W5, W6, W21, W23, W24, Y22,

AA5, AA6, AA22, AA25, AB7,

AB13, AB19, AB22, AC10,

AC12, AC16, AC20

VSS

——

No Connect

C22

—

Notes:

1. This pin is an open drain signal. A weak pull-up resistor (1 k

Ω) should be placed on this pin to OVDD.

2. This pin is an open drain signal. A weak pull-up resistor (2–10 k

Ω) should be placed on this pin to OVDD.

3. This output is actively driven during reset rather than being three-stated during reset.

4. These JTAG and local bus pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull up if the chip is in PCI host mode. Follow the PCI specification’s recommendation.

6. This pin must always be tied to GND. 7.This pin has weak internal pull-down N-FET that is always enabled.8.Though this pin

has weak internal pull-up yet it is recommended to apply an external pull-up.

Table 55. MPC8323E PBGA Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

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