MPC8321EVRADDC datasheet(71/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Thermal

22.7

Suggested PLL Configurations

To simplify the PLL configurations, the MPC8323E might be separated into two clock domains. The first

domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and

has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock

domains are independent, and each of their PLLs are configured separately. Both of the domains has one

common input clock. Table 63 shows suggested PLL configurations for 33, 25, and 66 MHz input clocks.

23 Thermal

This section describes the thermal specifications of the MPC8323E.

23.1

Thermal Characteristics

Table 64 provides the package thermal characteristics for the 516 27

× 27 mm PBGA of the MPC8323E.

Table 63. Suggested PLL Configurations

Conf No.

SPMF

Core

PLL

CEMF

CEDF

Input Clock

Frequency

(MHz)

CSB

Frequency

(MHz)

Core

Frequency

(MHz)

QUICC

Engine

Frequency

(MHz)

0100

0000100

0110

33.33

133.33

266.66

200

0100

0000101

1000

100

250

200

0010

0000100

0011

66.67

133.33

266.66

200

0100

0000101

0110

33.33

133.33

333.33

200

0101

0000101

1000

125

312.5

200

0010

0000101

0011

66.67

133.33

333.33

200

Table 64. Package Thermal Characteristics for PBGA

Characteristic

Board type

Symbol

Value

Unit

Notes

Junction-to-ambient natural convection

Single-layer board (1s)

RθJA

°C/W

1, 2

Junction-to-ambient natural convection

Four-layer board (2s2p)

RθJA

°C/W

1, 2, 3

Junction-to-ambient (@200 ft/min)

Single-layer board (1s)

RθJMA

°C/W

1, 3

Junction-to-ambient (@200 ft/min)

Four-layer board (2s2p)

RθJMA

°C/W

1, 3

Junction-to-board

—

RθJB

°C/W

Junction-to-case

—

RθJC

9°C/W

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