MPC8321EVRADDC datasheet(12/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

RESET Initialization

Table 10 provides the PLL lock times.

5.1

Reset Signals DC Electrical Characteristics

Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 9.

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to

negation of PORESET when the MPC8323E is in PCI host mode

4—

tCLKIN

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to

negation of PORESET when the MPC8323E is in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR config signals with respect to negation of

HRESET

0—

—

Time for the MPC8323E to turn off POR configuration signals with respect

to the assertion of HRESET

—4

Time for the MPC8323E to turn on POR configuration signals with respect

to the negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the

primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See

the

MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.

3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 10. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs—

Table 11. Reset Signals DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Notes

Output high voltage

VOH

IOH = –6.0 mA

2.4

—

Output low voltage

VOL

IOL = 6.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—

–0.3

0.8

—

Table 9. RESET Initialization Timing Specifications (continued)

Parameter/Condition

Min

Max

Unit

Notes

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