MPC8321EVRADDC datasheet(46/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

HDLC, BISYNC, Transparent, and Synchronous UART

Figure 38 provides the AC test load.

Figure 38. AC Test Load

Figure 39 and Figure 40 represent the AC timing from Table 51. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Inputs—External clock input hold time

tHEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs

internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

Table 52. Synchronous UART AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Outputs—Internal clock delay

tUAIKHOV

05.5

Outputs—External clock delay

tUAEKHOV

110

Outputs—Internal clock high impedance

tUAIKHOX

05.5

Outputs—External clock high impedance

tUAEKHOX

Inputs—Internal clock input setup time

tUAIIVKH

6—

Inputs—External clock input setup time

tUAEIVKH

4—

Inputs—Internal clock input hold time

tUAIIXKH

0—

Inputs—External clock input hold time

tUAEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUAIKHOX symbolizes the outputs

internal timing (UAI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are

invalid (X).

Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1 (continued)

Characteristic

Symbol2

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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