MPC8321EVRADDC datasheet(79/82 Pages) FREESCALE

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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Ordering Information

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these

pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize

the disruption of signal quality or speed for output pins thus configured.

24.7

Pull-Up Resistor Requirements

The MPC8323E requires high resistance pull-up resistors (10 k

Ω is recommended) on open drain type pins

including I2C pins, Ethernet Management MDIO pin, and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface,

see AN3361, “MPC8321E/MPC8323E PowerQUICC Design Checklist,” Rev. 1.

25 Ordering Information

This section presents ordering information for the devices discussed in this document, and it shows an

example of how the parts are marked. Ordering information for the devices fully covered by this document

is provided in Section 25.1, “Part Numbers Fully Addressed by This Document.”

25.1

Part Numbers Fully Addressed by This Document

Table 66 provides the Freescale part numbering nomenclature for the MPC8323E family. Note that the

individual part numbers correspond to a maximum processor core frequency. For available frequencies,

contact your local Freescale sales office. In addition to the maximum processor core frequency, the part

numbering scheme also includes the maximum effective DDR memory speed and QUICC Engine bus

frequency. Each part number also contains a revision code which refers to the die mask revision number.

Table 66. Part Numbering Nomenclature

MPC

nnnn

DCA

Product

Code

Part

Identifier

Encryption

Acceleration

Temperature

Range1

Package2

e300 Core

Frequency3

DDR

Frequency

QUICC

Engine

Frequency

Revision

Level

MPC

8323

Blank = Not

included

E = included

Blank = 0 to

105

°C

C = –40 to

105

°C

VR = Pb-free

PBGA

ZQ = Pb

PBGA

AD = 266 MHz

AF = 333 MHz

D = 266 MHz C = 200 MHz Contact local

Freescale

sales office

Notes:

1. Contact local Freescale office on availability of parts with C temperature range.

2. See Section 21, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification

support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core

frequencies.

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